Programmable integrated circuits are a type of integrated circuit that can be configured by a user to implement custom logic functions. In a typical scenario, a logic designer uses computer-aided design (CAD) tools to design a custom logic circuit. When the design process is complete, the CAD tools generate configuration data. The configuration data is loaded into a programmable integrated circuit to configure the device to perform desired logic functions.
In a typical system, a programmable integrated circuit, memory devices, and other electronic components are mounted on a printed circuit board. The programmable integrated circuit includes memory interface circuitry that is used to relay data back and forth between the programmable integrated circuit and the memory devices (i.e., the memory interface circuitry is used to read data from and write data into the memory devices).
With each new generation of transistor technology, memory circuits are operated at ever-increasing speeds. However, programmable integrated circuits have been unable to match the increases in clock speeds of memory circuits. For example, double-data-rate random access memory three (DDR3) may operate at 1333 MHz and double-data-rate random access memory four (DDR4) can operate at speeds of 800 MHz to 1600 MHz, whereas programmable integrated circuits may operate at reduced speeds of about 200-400 Mhz. Conventional memory interface circuitry accommodates mismatched system and memory clock signals by implementing so-called quarter rate and half rate conversion techniques in which the memory interface circuitry communicates with on-chip circuitry using a system clock signal that is one-fourth (i.e., quarter rate) or half (i.e., half rate) of the speed of the memory clock. However, conventional quarter rate and half rate memory interface circuitry require predefined mappings between each system clock cycle and a corresponding set of memory clock cycles. For example, a controller command received at a quarter rate system clock cycle is mapped to a predefined set of four memory clock cycles. Such predefined mappings between system and memory clock cycles can reduce flexibility in communications with memory.